Fuse links have been used for many years in digital integrated circuits, particularly programmable read-only memories (PROMS) and programmable logic arrays (PALS). The fuse links are used to connect matrices of circuit elements for custom applications or for permanent data storage, by selectively breaking unwanted fuse links. Fuse links ar broken by various techniques such as selectively applying a sufficiently large current through the unwanted links.
As with many other semiconductor products, increasing integration of devices on a single chip is rapidly obsoleting the processing techniques used to fabricate fuse link devices. Dry plasma etching is increasingly replacing wet chemical etching, providing an increased level of integration. Although dry plasma etching allows smaller device widths and pitches, it can damage sensitive components on the surface of the substrate by overetching. Hence, it is important to minimize interaction between the dry etch and surface components as much as possible.
Scalability is also an important criterion in semiconductor processing. A process which can be easily adapted to smaller components is one which has a high degree of scalability. Previously developed processes for forming a fused link are not adaptible to highly integrated circuits wherein the width of the interconnecting leads and the spaces between the interconnecting leads have substantially decreased.
Furthermore, competitive forces have applied pressure to reduce the price of semiconductor products. Therefore, it is important that semiconductor production be as efficient as possible. The cost of a semiconductor device is largely dependent upon the number of masking levels used in fabricating the device. Thus, it is desirable to reduce the number of masking levels, and the associated critical alignment tolerance required during masking. Previously developed techniques for fabricating fuse links have presented difficulties in reducing the number of mask levels and in reducing alignment tolerances.
Therefore, a need has arisen for a fuse link process which minimizes dry etch damage and over etch of sensitive layers on the surface of the substrate, reduces the number of masking levels and the associated critical alignment of tolerances required during masking, and offers a high degree of scalability by using dry processing as much as possible.